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基本説明
The emphasis is on building the knowledge and tools for the automatic generation of interconnect structures.
Full Description
Programmable Logic Devices (PLDs) have become the key implementation medium for the vast majority of digital circuits designed today. While the highest-volume devices are still built with full-fabrication rather than field programmability, the trend towards ever fewer ASICs and more FPGAs is clear. This makes the field of PLD architecture ever more important, as there is stronger demand for faster, smaller, cheaper and lower-power programmable logic. PLDs are 90% routing and 10% logic. This book focuses on that 90% that is the programmable routing: the manner in which the programmable wires are connected and the circuit design of the programmable switches themselves. Anyone seeking to understand the design of an FPGA needs to become lit erate in the complexities of programmable routing architecture. This book builds on the state-of-the-art of programmable interconnect by providing new methods of investigating and measuring interconnect structures, as well as new programmable switch basic circuits. The early portion of this book provides an excellent survey of interconnec tion structures and circuits as they exist today. Lemieux and Lewis then provide a new way to design sparse crossbars as they are used in PLDs, and show that the method works with an empirical validation. This is one of a few routing architecture works that employ analytical methods to deal with the routing archi tecture design. The analysis permits interesting insights not typically possible with the standard empirical approach.
Contents
1. Introduction.- 2. Interconnection Networks.- 3. Models, Methodology and CAD Tools.- 4. Sparse Crossbar Design.- 5. Sparse Cluster Design.- 6. Routing Switch Circuit Design.- 7. Switch Block Design.- 8. Conclusions.- Appendices.- A Switch Blocks: Reduced Flexibility.- A.1 Introduction.- A.4 Results.- A.5 Summary.- B Switch Blocks: Diverse Design Instances.- C VPRx: VPR Extensions.- C.1 Determination of Router Effort.- C.2 Routing Graph and Netlist Changes (Sparse Clusters).- C.3 Area and Delay Calculation Improvements.- C.4 Runtime Improvements.- C.5 Experimental Noise Reduction.- C.6 Correctness Changes.- References.
