Ｓｙｓｔｅｍ Ｖｅｒｉｌｏｇ設計：バードウェア設計とモデリング・ガイド SystemVerilog For Design : A Guide to Using SystemVerilog for Hardware Design and Modeling （2003. 402 p.）

Sutherland, Stuart/ Davidmann, Simon/ Flake, Peter

SPRINGER NETHERLANDS（2003発売）

• 製本 Hardcover:ハードカバー版／ページ数 402 p.
• 言語 ENG
• 商品コード 9781402075308

基本説明

Addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and more.

Full Description

SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, "SystemVerilog for Design", addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, "SystemVerilog for Verification", covers the second aspect of SystemVerilog.