Substrate Noise Coupling in Mixed-Signal Asics

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Substrate Noise Coupling in Mixed-Signal Asics

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  • 製本 Hardcover:ハードカバー版／ページ数 288 p.
  • 言語 ENG
  • 商品コード 9781402073816
  • DDC分類 621.395

基本説明

Provides an overview of very recent research results in the field of substrate noise analysis and reduction techniques.

Full Description

This book is the first in a series of three dedicated to advanced topics in Mixed-Signal IC design methodologies. It is one of the results achieved by the Mixed-Signal Design Cluster, an initiative launched in 1998 as part of the TARDIS project, funded by the European Commission within the ESPRIT-IV Framework. This initiative aims to promote the development of new design and test methodologies for Mixed-Signal ICs, and to accelerate their adoption by industrial users. As Microelectronics evolves, Mixed-Signal techniques are gaining a significant importance due to the wide spread of applications where an analog front-end is needed to drive a complex digital-processing subsystem. In this sense, Analog and Mixed-Signal circuits are recognized as a bottleneck for the market acceptance of Systems-On-Chip, because of the inherent difficulties involved in the design and test of these circuits. Specially, problems arising from the use of a common substrate for analog and digital components are a main limiting factor. The Mixed-Signal Cluster has been formed by a group of 11 Research and Development projects, plus a specific action to promote the dissemination of design methodologies, techniques, and supporting tools developed within the Cluster projects. The whole action, ending in July 2002, has been assigned an overall budget of more than 8 million EURO.

Contents

Technology Impact on Substrate Noise.- Substrate Noise Generation in Complex Digital Systems.- Modeling and Analysis of Substrate Noise Coupling in Mixed-Signal ICs.- SPACE for Substrate Resistance Extraction.- Models and Parameters for Crosstalk Simulation.- High-Level Simulation of Substrate Noise Generation in Complex Digitlal Systems.- Modeling the Impact of Digital Substrate Noise on Analog Integrated Circuits.- Measuring and Modeling the Effects of Substrate Noise on the LNA for a CMOS GPS Receiver.- A Practical Approach to Modeling Silicon-Crosstalk in Systems-on-Silicon.- The Reduction of Switching Noise Using CMOS Current Steering Logic.- Low-Noise Digital Design Techniques.- How to Deal with Substrate Bounce in Analog Circuits in Epi-Type CMOS Technology.- Reducing Substrate Bounce in CMOS RF-Circuitry.