Pci-X System Architecture (Pc System Architecture) （PAP/CDR）

Pci-X System Architecture (Pc System Architecture) （PAP/CDR）

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  • 製本 Paperback:紙装版/ペーパーバック版／ページ数 688 p.
  • 言語 ENG
  • 商品コード 9780201726824
  • DDC分類 004.22

Full Description


The PCI-X bus will start appearing in advanced PCs within months, delivering breakthrough performance, transfer rates of up to 1.06 Gb/sec, and backward compatibility with the PCI standard. Now, there's a comprehensive guide to PCI-X, covering everything engineers and developers need to create robust, reliable PCI-X boards and software. As with all MindShare books, PCI-X System Architecture is written in an accessible, tutorial style proven to train engineers. It's based on MindShare's leading edge PCI-X course, and reflects extensive feedback and insights from hundreds of working professionals. The book presents detailed descriptions of every aspect of the PCI-X specification, including: device types and bus initialization, error detection and handling, split completion messages, and 64-bit transactions. It offers in-depth coverage of device enumeration and configuration; traffic analysis and load tuning, PCI-X bridges, electrical issues, and much more. For all computer hardware and software design engineers, and for all developers concerned with advanced PC hardware.

Contents

About This Book. I. BASIC CONCEPTS. 1. PCI Needed Improvement. 2. PCI-X Improves on PCI. 3. Bus Protocol/Speed = Lowest Common Denominator. 4. Device Types and Bus Initialization. 5. PCI-X Is a Registered Bus. 6. Intro to Commands. 7. Intro to Transaction Phases. 8. Intro to Transaction Termination. 9. Intro to Split and Immediate Transactions. II. TRANSACTION PROTOCOL. 10. Bus Arbitration. 11. Detailed Command Description. 12. Latency Rules. 13. The Address, Attribute, and Response Phases. 14. Dword Transactions. 15. Burst Transactions. 16. Transaction Terminations. 17. Split Completion Messages. 18. 64-Bit Transactions. 19. Parity Generation and Checking III. DEVICE CONFIGURATION. 20. Configuration Transactions. 21. Non-Bridge Configuration Registers. 22. Bridge Configuration Registers IV. LOAD TUNING. 23. Load Tuning Mechanisms V. PCI-X BRIDGES. 24. PCIX-to-PCIX Bridges. 25. Locked Transaction Series VI. ERROR DETECTION AND HANDLING. 26. Error Detection and Handling VII. ELECTRICAL ISSUES. 27. Electrical Issues. Appendix A: Protocol Rules. Appendix B: Glossary. Index.